IEEE

Implementation of FPGA-based Neural Network Controller for Reducing Speed Ripple for a PMSM-driven EV using MRAS Speed Estimator

Abstract: The conventional model reference adaptive system (MRAS) employs a proportional-integral (PI) controller with a low-pass filter (LPF). However, the LPF and integrator add phase delay and DC ...
IEEE

Implementation of XOR Gate using AOI model by Reconfigurable Artificial Neural Network on FPGA

Abstract: In this paper, we utilize a reconfigurable artificial neural network (RANN) to design digital logic gates, which serve as the fundamental components of a digital subsystem. We achieve ...